Protocol/IP Validation on FPGA Platform for a RISCV SoC
Protocol/IP Validation on FPGA Platform for a RISCV SoC
2 PagesHappiest Minds provided a solution for prototype validation of USB3.0, USB OTG, and HEVC video codec IPs on an FPGA platform for a RISC-V SoC. The project involved Verilog code porting, performance testing, and integration of USB 2.0 and USB 3.0 drivers with U-Boot and Linux. Key accomplishments included achieving timing closure on high-resource utilization FPGA and customizing drivers from the mainline kernel. The solution enabled pre-silicon validation, identifying RTL bugs before SoC tape-out, ensuring successful demonstration of USB use cases and complete SoC prototyping on the FPGA platform.
