WHITE PAPER page 1 of 6 Netronome Systems, Inc. 1. INTRODUCTION The increasing rate of change in protocols and algorithms related to networking, security and machine learning, coupled with the slowing down of Moore’s Law have prompted growing interest in coprocessor-based SoCs to offload and accelerate domain-specific workloads. Data movement efficiency across the processing cores and memory in such SoC designs is becoming paramount. Coprocessor architectures need to be scalable to handle performance requirements both at the edge and core of the network. Lower development costs are needed for implementations to adapt to multiple domains and workload evolution. Netronome has developed a composable architecture in which cross-chip functions are implemented across a distributed set of

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